Lead DFT Engineer

Key Responsibilities:

• Define and implement end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan, and MBIST.
• Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
• Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST, collaborating with cross-functional teams.

Technical Requirements:

• 12+ years in DFT with at least 2 years in a leadership role; Bachelor’s degree in a related field.
• Mastery of industry-standard tools (Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus).
• Deep expertise in MBIST with repair, IJTAG, boundary scan, and experience with FinFET nodes (7nm, 5nm, or below).

What You'll Do:

• Lead post-silicon validation and debug on ATE to root-cause silicon failures and optimize test time.
• Manage DFT in multi-voltage/power-gated designs for edge efficiency.
• Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage with minimal area and power impact.