Midcore CPU Performance Architect

Tenstorrent is seeking a CPU Architect to spearhead the design and optimization of the Midcore Unit (MC) within their high-performance, out-of-order RISC-V CPUs. This role offers hands-on architectural involvement, directly influencing instruction scheduling and execution units critical to CPU performance. You will model, simulate, and evaluate mid-core performance and PPA (power, performance, area) tradeoffs, including novel cross-unit instruction scheduling and execution techniques. The role involves proposing and prototyping new approaches to optimize scheduling and execution paths and improve instruction/data throughput. Collaboration with software, RTL, and performance modeling teams will be essential for realizing real-world performance gains. The position offers opportunities to learn how to architect high-throughput, low-latency solutions for general-purpose, AI, and HPC workloads, model and optimize CPU behavior across diverse instruction-mix patterns, and deliver innovative performance features from architecture to implementation.