Own RTL to GDS physical implementation flows including synthesis, floor-planning, place and route, clock tree synthesis, timing/power closure, EM/IR, and PD sign-off.
Own physical design and implementation of high-performance designs from block level to system level components.
Collaborate with micro-architects on performance, power, and area trade-offs and develop methodologies for physical implementation.
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, and Synthesis.
Work closely with PD, DV, and software teams to achieve PPA goals, functional coverage, and optimal performance.
Debug silicon-level functional, timing, and power issues during bring up.
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs, delivering industry-leading training and inference speeds. It works with leading model labs and global enterprises, with recent partnerships including OpenAI, and fosters a simple, non-corporate culture that values individual beliefs.
Define, design, verify, and document ASIC/FPGA developments, including architecture, system simulation, and detailed design approaches.
Evaluate process flows such as synthesis, place and route, timing, and power utilization, and create test and simulation plans.
Lead technical proposals, review vendor capabilities, and serve as a consultant to management and customers on complex engineering applications.
General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products and services for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, alignment and transparency, and offer a flexible work environment.