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About the Role:
- As a senior front-end design engineer, you will be a key part of the team designing next-gen Wafer Scale Engine chips.
- This role requires deep expertise in RTL design and integration for high-performance, power-efficient solutions.
- You will collaborate with design verification, physical design, software, and system teams.
Responsibilities:
- Drive chip design aspects: Functional Spec, Micro-architecture, RTL development, Synthesis.
- Work closely with PD team for design closure to meet PPA goals.
- Collaborate with DV and DFT teams for functional and test coverage.
- Work with software and system teams to optimize performance and features.
- Debug silicon-level issues during bring up.
Requirements:
- Master’s degree in CS, EE, or equivalent.
- 8+ years in delivering complex RTL designs.
- Experience with front-end chip integration and third-party IP.
- Proven track record of multiple silicon successes.
- Knowledge of networking stack, PCIe, CPU interfaces, and Serdes.
- Proficiency in scripting tools: Python, TCL.
Cerebras Systems
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs, delivering industry-leading training and inference speeds. It works with leading model labs and global enterprises, with recent partnerships including OpenAI, and fosters a simple, non-corporate culture that values individual beliefs.