Similar Jobs

See all

Front End Design Verification Engineer

Tenstorrent

North America

SystemVerilog UVM C/C++

Staff Engineer - Design Verification

Partner Company

India

SystemVerilog UVM

Senior Front-End Design Engineer

Cerebras Systems

US

Python

About the Role:

  • Verify the next generation of high-performance RISC-V CPU cores.
  • Develop verification strategies and test environments.

What You Will Do:

  • Write test plans and architect test benches.
  • Debug failures and drive issues to closure.

What We Look For:

  • 6+ years of experience in design verification for CPUs or complex digital designs.
  • Strong experience with SystemVerilog, UVM, and CPU architecture.
  • Proficiency in C/C++ or Python and collaboration skills.

Tenstorrent

Tenstorrent is a leader in AI technology, developing high-performance RISC-V CPUs and AI platforms. The company values collaboration, curiosity, and solving hard problems, and is growing its team with contributors of all seniorities.

Apply for This Position