Verify the fetch unit for next-gen high-performance RISC-V CPU cores, including instruction fetch, prediction, decode, and dispatch.
Develop verification strategies, create sophisticated tests, and debug complex failures using SystemVerilog and UVM.
Collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads and corner cases.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.
Define and lead scalable verification strategies for PCIe, CXL, Ethernet, and UCIe subsystems.
Architect reusable UVM environments, testbenches, and verification components for high-speed protocols.
Drive coverage closure, debug across simulation and silicon, and mentor verification engineers.
They develop next-generation semiconductor infrastructure for AI and HPC, specializing in high-speed interconnect IP and SoC verification. The team is fast-paced, globally distributed, and collaborative with minimal bureaucracy.
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, and Synthesis.
Work closely with PD, DV, and software teams to achieve PPA goals, functional coverage, and optimal performance.
Debug silicon-level functional, timing, and power issues during bring up.
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs, delivering industry-leading training and inference speeds. It works with leading model labs and global enterprises, with recent partnerships including OpenAI, and fosters a simple, non-corporate culture that values individual beliefs.