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Front End Design Verification Engineer

Tenstorrent
North America Spain

  • Verify the fetch unit for next-gen high-performance RISC-V CPU cores, including instruction fetch, prediction, decode, and dispatch.
  • Develop verification strategies, create sophisticated tests, and debug complex failures using SystemVerilog and UVM.
  • Collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads and corner cases.

SystemVerilog C/C++ Python
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Staff Engineer - Design Verification

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  • Define and lead scalable verification strategies for PCIe, CXL, Ethernet, and UCIe subsystems.
  • Architect reusable UVM environments, testbenches, and verification components for high-speed protocols.
  • Drive coverage closure, debug across simulation and silicon, and mentor verification engineers.

They develop next-generation semiconductor infrastructure for AI and HPC, specializing in high-speed interconnect IP and SoC verification. The team is fast-paced, globally distributed, and collaborative with minimal bureaucracy.

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