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See allResponsibilities:
- Lead verification strategy for PCIe, CXL, Ethernet, and UCIe subsystems.
- Build reusable UVM environments and drive coverage closure.
Requirements:
- 8+ years in SoC/IP verification with SystemVerilog and UVM.
- Deep expertise in high-speed protocols like PCIe, CXL, and UCIe.
Benefits:
- Remote-friendly role with high technical ownership.
- Work on AI/HPC semiconductor infrastructure with global teams.
Partner Company
They develop next-generation semiconductor infrastructure for AI and HPC, specializing in high-speed interconnect IP and SoC verification. The team is fast-paced, globally distributed, and collaborative with minimal bureaucracy.