Front End Design Verification Engineer

Responsibilities:

• Verify the fetch unit for next-gen high-performance RISC-V CPU cores, including instruction fetch, prediction, decode, and dispatch.
• Develop verification strategies, create sophisticated tests, and debug complex failures using SystemVerilog and UVM.
• Collaborate with CPU architects and RTL designers to ensure front-end correctness across workloads and corner cases.

Qualifications:

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.

Opportunities:

• Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU.
• Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently.
• Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.