Principal Engineer - SoC Design Lead

The Principal Engineer - SoC Design Lead will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an SoC design. Responsibilities include integrating logic of IP blocks and subsystems into a full chip SoC or discrete component design. The candidate will participate in the definition of architecture and microarchitecture features of the block being designed. The role involves performing quality checks, applying strategies to optimize logic to meet power, performance, area, and timing goals, and reviewing verification plans. Following secure development practices to address the security threat model and security objects within the design is crucial. Working with IP providers to integrate and validate IPs at the SoC level, driving quality assurance compliance for smooth IPSoC handoff, and mentoring other technical leaders are also key aspects of this position.