Sr. ASIC Design Verification Engineer

Groq is seeking a Design Verification Engineer to join their Hardware team, where you will work closely with internal interdisciplinary teams to drive key aspects of ASIC verification in a dynamic, fast-paced environment. Responsibilities include verifying hardware features of Language Process Unit (LPU), collaborating within the Hardware Team to design and verify features on LPU chips in simulation, emulation and silicon, and implementing and optimizing automated verification flows to improve productivity and efficiency. The ideal candidate will have experience with building block and SOC testbench development, SystemVerilog and UVM, randomly constrained testing methodologies, power verification strategies and UPF, netlist simulation, formal verification flow and tools, and Python and/or Perl scripting.