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ASIC Verification Engineer - ARM

Snap

Global

SystemVerilog SystemVerilog

WHAT YOU’LL DO:

  • Develop verification plans and author SystemVerilog Assertions.
  • Build functional coverage models and ensure verification meets safety standards.
  • Debug failures and collaborate with design engineers.

REQUIRED QUALIFICATIONS:

  • Bachelor’s degree in Electrical Engineering or related field and 2+ years of experience.
  • Proficient in SystemVerilog, industry simulators, and Git-based collaborative workflows.
  • Strong communication and teamwork skills.
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