Senior DFT Engineer

Responsibilities:

• Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
• Collaborate with RTL, verification, and physical design teams to integrate DFT solutions.
• Support silicon bring-up and debug to optimize test coverage.

Qualifications:

• Minimum of 5 years in DFT engineering with complex SoC projects.
• Strong problem-solving skills and passion for semiconductor innovation.
• Familiarity with IEEE 1149.x / 1500 / 1687 standards.

Culture:

• Dynamic and fast-growing international organization.
• Open culture that supports creativity and continual innovation.
• Collaborative ownership and freedom with responsibility.