Principal IC Layout Engineer

Responsible for the physical layout of integrated circuits from initial floorplanning to final tape-out, ensuring designs meet all performance, power, area, and reliability targets. This role requires a strong understanding of semiconductor device physics, advanced process technologies, and a keen eye for detail. Will perform physical layout of complex analog / mixed-signal circuits, adhering to design specifications and foundry design rules (DRC/LVS). Collaborates closely with circuit design engineers to understand design requirements. Will conduct detailed floorplanning and pin planning to optimize interconnects. Implements critical analog matching, shielding, and guarding techniques to mitigate noise. Utilizes advanced layout techniques for minimizing electromigration (EM), IR drop, and latch-up concerns. Performs comprehensive design rule checking (DRC), layout versus schematic (LVS), and parasitic extraction (PEX) using industry-standard EDA tools. Analyzes extracted parasitics and provide feedback to circuit designers for design optimization. Generates and verify GDSII files for tape-out, ensuring all necessary layers and information are included. Develops and maintains layout methodologies, scripts, and documentation to improve efficiency and quality.