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Responsibilities:
- Define HW architecture and evaluate design trade-offs for performance, area, and power.
- Lead RTL development, integration, and verification throughout the design cycle.
- Partner with firmware and verification teams to ensure top-quality silicon delivery.
Qualifications:
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
Preferred / Plus:
- Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
- Familiarity with UVM-based verification environments.
- Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
FortifyIQ
They are looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. They aim to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.