Verification Engineer

Responsibilities:

• Understand chip and subsystem architecture.
• Develop, maintain, and extend UVM-based verification environments.
• Write test plans, test cases, and sequences for block- and chip-level verification.

Qualifications:

• BSEE/MSEE or equivalent in Electrical Engineering, Computer Science, or a related field.
• Proficient in Verilog/SystemVerilog and UVM.
• Comfortable working in Linux and with industry-standard EDA tools.

Preferred Skills:

• Strong problem-solving and analytical skills.
• Experience with functional and code coverage analysis.