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Who You Are:
- Experienced with bringing ASICs from design phase through production ramp, managing wafer yield, and analyzing field failure rates.
- Able to translate system and safety requirements into concrete constraints on package architecture, DFT insertion, and ATE or SLT test content.
- Confident working directly with foundry, OSAT, and ATE vendors to debug issues.
What We Need:
- Define test strategy for multi chiplet packages from initial silicon through high volume production.
- 10+ years of experience working across multiple teams and multiple companies to coordinate test, yield, and quality efforts.
- Feed lessons learned back into next generation SiP architectures, DFT strategy, and test content.
What You Will Learn:
- How to bring a SiP to high volume, automotive grade production.
- How chiplets, RISC V CPUs, AI accelerators, and die to die links come together in a unified automotive platform.
- How to trade off package architecture, DFT, and test cost to hit aggressive performance, quality, and reliability targets.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.