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Role Overview:
- We're seeking an experienced RTL Verification Engineer to ensure functionality and quality of complex digital designs across ASIC and FPGA platforms.
- This role focuses on building robust verification environments and executing coverage-driven verification plans.
Key Responsibilities:
- Develop and maintain UVM-based verification environments, creating directed and constrained-random test cases.
- Analyze simulation results, debug complex issues, and track functional/code coverage to closure.
- Automate regression testing with Python and enhance verification infrastructure.
Qualifications:
- 7+ years of digital design verification experience with strong UVM and SystemVerilog skills.
- Experience with EDA tools like Synopsys VCS, Mentor Questa, or Cadence Xcelium and protocols like PCIe, Ethernet, AXI.
- Strong analytical, communication, and collaboration skills for cross-functional teams.
Compensation & Culture:
- Target base salary ranges from $160,000 to $240,000 per year plus meaningful equity and 401(k).
- We operate with unity, trust, and mutual accountability across remote and on-site locations in the U.S. and Canada.
Delos Data Inc.
Delos Data builds foundational technology for performance, scalability, and resiliency in large-scale AI data center clusters. The startup is backed by top-tier VCs, led by experienced founders, and operates with a culture of unity, trust, and accountability across the U.S. and Canada.