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Key Responsibilities:
- Lead DFT architecture, implementation & sign-off for complex ASIC/SoC designs.
- Drive scan insertion, scan chains, and compression flows.
- Own MBIST/LBIST integration and debug.
Requirements:
- 10+ years of hands-on ASIC DFT experience.
- Expertise in scan, ATPG, MBIST, JTAG, and debug tools.
- Experience with Synopsys/Cadence/Siemens tools.
Preferred Qualifications:
- Knowledge of Tessent/SSN tools and yield analysis.
- Multi-node ASIC experience.
- Post-silicon validation and hierarchical DFT exposure.
Peru
Peru is a company with open roles across various teams. The company culture aligns with remote work and values technical expertise in ASIC engineering.