Principal SOC Physical Verification & Integration Specialist

Responsibilities:

• Drive full-chip physical assembly of large-scale SOCs, managing top-level floorplanning, bump planning, and global power grid integration.
• Architect and deploy hierarchical physical verification flows, defining boundary conditions and interface rules.
• Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using Siemens Calibre.

Collaboration:

• Partner with Physical Design and STA teams to resolve integration conflicts and timing issues.
• Work directly with foundry partners to interpret complex design rules and waive edge-case violations.

Qualifications:

• 14+ years in SOC physical design and verification, with tapeout experience on large, complex SOCs.
• Deep understanding of RTL-to-GDSII flow, expert knowledge of physical integration, and proficiency in tools like Cadence Innovus and Siemens Calibre.
• High proficiency in Tcl, Python, or Perl for automation.