Source Job

• Architect, develop, and maintain highly automated RTL-to-GDSII and timing signoff flows.
• Drive advanced physical design methodologies in Cadence Innovus to maximize PPA.
• Own STA and timing signoff methodology using Cadence Tempus, including DMSA and ECO flows.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. Launched in 2022, it is an ambitious startup led by veteran technologists with backgrounds in semiconductor design and AI systems.

• Develop and execute verification plans for mixed signal components, ensuring comprehensive coverage against architectural and microarchitectural specifications.
• Build and maintain test benches and verification environments to validate functionality, timing, and power requirements.
• Create analog behavioral models and system simulation models, and collaborate with cross-functional teams to debug and resolve issues.

Intel is a global leader in semiconductor design and manufacturing, delivering technologies that power computing and innovation. The Central Engineering Group builds scalable engineering solutions across product enablement, custom ASIC, and foundry enablement, with a focus on customer-driven end-to-end solutions.

• Lead DFT architecture, implementation, and sign-off for complex ASIC/SoC designs.
• Drive scan insertion, MBIST/LBIST integration, and silicon debug for failure analysis.
• Collaborate with cross-functional teams including RTL, PD, STA, and validation.

Peru is a company with open roles across various teams. The company culture aligns with remote work and values technical expertise in ASIC engineering.