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Responsibilities:
- Design and implement low-latency RTL modules in SystemVerilog.
- Develop FPGA/ASIC logic for signal processing and real-time control.
- Own RTL lifecycle from architecture to verification.
Requirements:
- BS/MS in EE/CE or equivalent, 4+ years FPGA/ASIC design.
- Strong SystemVerilog and microarchitecture skills.
- Experience with synthesis, STA, and CDC.
Nice to Have:
- AMD/Xilinx Versal experience.
- Familiarity with AXI, PCIe, DDR interfaces.
- Python/Tcl scripting.
Confidential Client
The company develops advanced control and measurement systems for quantum computing, enabling precise real-time control of complex quantum systems. It works in an international engineering environment focused on FPGA and ASIC-based platforms.