Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
Translate architectural specifications into clean, efficient, and scalable microarchitectures
We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.
Define, design, verify, and document ASIC/FPGA developments, including architecture, system simulation, and detailed design approaches.
Evaluate process flows such as synthesis, place and route, timing, and power utilization, and create test and simulation plans.
Lead technical proposals, review vendor capabilities, and serve as a consultant to management and customers on complex engineering applications.
General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products and services for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, alignment and transparency, and offer a flexible work environment.
Develop custom IP for new features of the Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors and lead engineers to integrate new functionality and develop future satellite communications and network architecture
Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. With 33 satellites launched to date, Kepler is a dedicated team of engineers building the next generation of spacecraft in an innovative and inclusive environment.
Responsible for definition, design, verification and documentation for ASIC and FPGA developments.
Develops test and simulation plans, verifies results, and analyzes performance using SystemVerilog, UVM, and formal methods.
Supports the generation of technical engineering products throughout the ASIC/FPGA development life cycle.
General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, and transparency, offering a flexible work environment.
Design and implement FPGA code for Kepler's satellite digital payloads, focusing on DSP algorithms for software-defined radios or embedded systems.
Participate in all phases of FPGA design flow, from simulation and synthesis through timing closure and hardware testing.
Collaborate with lead engineers on communications architecture and integrate IP cores for new satellite constellation features.
Kepler Communications operates the first commercial optical data relay constellation, providing real-time, on-orbit connectivity for critical missions. With 33 satellites launched and a Great Place to Work certification for seven years, the company fosters a culture of bold thinkers and passionate problem-solvers.
Design and implement FPGA-based digital systems to meet functional, performance, and reliability requirements.
Translate system-level specifications into efficient digital architectures, including coding, synthesis, simulation, and timing closure.
Collaborate with cross-functional teams to integrate, verify, and debug FPGA designs for advanced communication platforms.
The company develops advanced digital hardware and communications technology solutions. It fosters a collaborative, innovation-driven environment with multidisciplinary engineering teams.
Develop and maintain UVM-based verification environments for complex ASIC and FPGA designs.
Create and execute coverage-driven verification plans, test cases, and SystemVerilog Assertions.
Collaborate with RTL engineers to debug issues, analyze coverage, and drive verification to closure.
Delos Data builds foundational technology for performance, scalability, and resiliency in large-scale AI data center clusters. The startup is backed by top-tier VCs, led by experienced founders, and operates with a culture of unity, trust, and accountability across the U.S. and Canada.
You will walk us through your approach to RTL implementation and hardware description.
You will review and react to specific automated evaluation scenarios.
You will describe a recent time you tackled a complex hardware verification challenge.
Terac is building the world's largest pool of vetted human experts for AI. Researchers, AI labs, and product teams use Terac to recruit, screen, and pay study participants across industries.
Own RTL to GDS physical implementation flows including synthesis, floor-planning, place and route, clock tree synthesis, timing/power closure, EM/IR, and PD sign-off.
Own physical design and implementation of high-performance designs from block level to system level components.
Collaborate with micro-architects on performance, power, and area trade-offs and develop methodologies for physical implementation.
Baya Systems is a fast-moving Series B startup accelerating intelligent computing in the emerging chiplet era with software-driven fabric solutions and semiconductor IP. Built by serial entrepreneurs, it seeks energetic, dedicated individuals passionate about enabling innovation in the semiconductor industry.