Develop and maintain UVM-based verification environments for complex ASIC and FPGA designs.
Create and execute coverage-driven verification plans, test cases, and SystemVerilog Assertions.
Collaborate with RTL engineers to debug issues, analyze coverage, and drive verification to closure.
Delos Data builds foundational technology for performance, scalability, and resiliency in large-scale AI data center clusters. The startup is backed by top-tier VCs, led by experienced founders, and operates with a culture of unity, trust, and accountability across the U.S. and Canada.
Work with cross-functional teams to deliver embedded processing solutions for communications and networking.
Own the FPGA firmware lifecycle from MATLAB/Simulink algorithms through architecture, integration, and test.
Establish HDL workflows and best practices for simulation, verification, and system testing.
Anduril Industries is a defense technology company transforming U.S. and allied military capabilities with advanced technology, including an AI-powered operating system called Lattice OS. The company brings a fast-paced, mission-driven culture focused on delivering cutting-edge autonomy, AI, and sensor fusion to the military.
Develop custom IP for new features of the Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors and lead engineers to integrate new functionality and develop future satellite communications and network architecture
Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. With 33 satellites launched to date, Kepler is a dedicated team of engineers building the next generation of spacecraft in an innovative and inclusive environment.
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, and Synthesis.
Work closely with PD, DV, and software teams to achieve PPA goals, functional coverage, and optimal performance.
Debug silicon-level functional, timing, and power issues during bring up.
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs, delivering industry-leading training and inference speeds. It works with leading model labs and global enterprises, with recent partnerships including OpenAI, and fosters a simple, non-corporate culture that values individual beliefs.
Responsible for definition, design, verification and documentation for ASIC and FPGA developments.
Develops test and simulation plans, verifies results, and analyzes performance using SystemVerilog, UVM, and formal methods.
Supports the generation of technical engineering products throughout the ASIC/FPGA development life cycle.
General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, and transparency, offering a flexible work environment.
Work closely with CPU architects, RTL designers, and software engineers to develop verification strategies.
Build robust test environments and uncover corner cases in modern out-of-order processors.
Own meaningful portions of the verification effort from test plans to debugging failures.
Tenstorrent is a leader in AI technology, developing high-performance RISC-V CPUs and AI platforms. The company values collaboration, curiosity, and solving hard problems, and is growing its team with contributors of all seniorities.