Develop custom IP for new features of the Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors and lead engineers to integrate new functionality and develop future satellite communications and network architecture
Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. With 33 satellites launched to date, Kepler is a dedicated team of engineers building the next generation of spacecraft in an innovative and inclusive environment.
Design and implement FPGA code for Kepler's satellite digital payloads, focusing on DSP algorithms for software-defined radios or embedded systems.
Participate in all phases of FPGA design flow, from simulation and synthesis through timing closure and hardware testing.
Collaborate with lead engineers on communications architecture and integrate IP cores for new satellite constellation features.
Kepler Communications operates the first commercial optical data relay constellation, providing real-time, on-orbit connectivity for critical missions. With 33 satellites launched and a Great Place to Work certification for seven years, the company fosters a culture of bold thinkers and passionate problem-solvers.
Work with cross-functional teams to deliver embedded processing solutions for communications and networking.
Own the FPGA firmware lifecycle from MATLAB/Simulink algorithms through architecture, integration, and test.
Establish HDL workflows and best practices for simulation, verification, and system testing.
Anduril Industries is a defense technology company transforming U.S. and allied military capabilities with advanced technology, including an AI-powered operating system called Lattice OS. The company brings a fast-paced, mission-driven culture focused on delivering cutting-edge autonomy, AI, and sensor fusion to the military.
Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
Translate architectural specifications into clean, efficient, and scalable microarchitectures
We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.