$100,000–$500,000
USD/year
Assist in the design and optimization of memory subsystems, including cache hierarchies, coherence protocols, and memory controllers. Contribute to the development of high-performance interconnect architectures, including on-chip networks and chip-to-chip interfaces. Perform simulations, modeling, and performance analysis of memory and interconnect components. Collaborate with hardware and software teams to optimize memory access patterns and system performance.