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Key Responsibilities:
- Participate in design development tasks.
- Develop logic designs and RTL coding.
- Optimize logic to meet IP release requirements.
Qualifications:
- Bachelor's or Master's in Electrical or Computer Engineering.
- Experience with System Verilog and VCS/Synopsys simulators.
- Programming experience in C/C++/Perl/Python/TCL/Unix Shell script.
Altera
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity and AI acceleration. They empower engineers to design and deploy advanced systems with unmatched flexibility and performance, contributing to shaping the future through innovation.