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Key Responsibilities:
- Guarantee RTL designs are matching specifications and requirements.
- Define, implement and execute verification plans to ensure the designs meet quality and performance goals.
- Build and maintain automated verification environments.
Qualifications/Skills:
- Degree in electronics engineering, electrical engineering, computer science or other relevant discipline.
- Minimum of 3 years of experience in ASIC or FPGA verification.
- Proficiency in SystemVerilog, C/C++ or Python for designing and implementing testbenches.
Axelera AI
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, and are headquartered at the High Tech Campus in Eindhoven, Netherlands with offices across Europe.