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Key Responsibilities:
- Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
- Collaborate with RTL, verification, and physical design teams to integrate DFT solutions efficiently.
- Support silicon bring-up and debug, helping to optimize test coverage and yield.
Qualifications:
- Minimum of 5 years in DFT engineering, preferably with complex SoC projects.
- Skills in SystemVerilog RTL, TCL, Python, Unix/Linux workflows.
- Core Knowledge: Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification.
Axelera AI
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, with offices in multiple European countries and are headquartered in Eindhoven, Netherlands.