Build and debug emulation models from RTL designs using synthesis, partitioning, and routing tools.
Develop automation tools and workflows to streamline emulation setup and increase verification efficiency.
Collaborate with design, validation, and software teams to resolve complex technical issues and support SoC bring-up.
This company focuses on SoC and IP development using hardware emulation and verification for next-generation silicon. The team is collaborative and high-impact, working with advanced emulation platforms and multidisciplinary engineering teams.
Design and implement FPGA code for Kepler's satellite digital payloads, focusing on DSP algorithms for software-defined radios or embedded systems.
Participate in all phases of FPGA design flow, from simulation and synthesis through timing closure and hardware testing.
Collaborate with lead engineers on communications architecture and integrate IP cores for new satellite constellation features.
Kepler Communications operates the first commercial optical data relay constellation, providing real-time, on-orbit connectivity for critical missions. With 33 satellites launched and a Great Place to Work certification for seven years, the company fosters a culture of bold thinkers and passionate problem-solvers.
Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
Translate architectural specifications into clean, efficient, and scalable microarchitectures
We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.