ASIC Synthesis and Timing Engineer

Responsibilities:

• Work on the RTL-to-Synthesis flow.
• Collaborate with front-end engineers to assure timing closure, and efficient design iteration.
• Manage and technically guide external physical design partners and service vendors.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with Synthesis, constraints development

Nice to Have:

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.