Source Job

$130,000–$200,000/yr
US

  • Develop the timing constraints and validate them—from RTL handoff to synthesis.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).

Communication

3 jobs similar to ASIC Synthesis and Timing Engineer

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$200,000–$280,000/yr
US

  • Lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
  • Own the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp.
  • Operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors, we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

$180,000–$260,000/yr
US

  • Define ASIC package architecture for FC-BGA and MCM solutions.
  • Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
  • Establish package design standards, methodologies, and best practices.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors, they're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

$120,000–$400,000/yr
US 4w PTO 12w maternity

  • Lead SoC architecture by translating Product Requirements Documents (PRDs) into SoC-level architectures in collaboration with subsystem architects and cross-functional teams
  • Define SoC architecture including memory, systems, interconnects, clocking, power, IP requirements, and system integration
  • Own architectural specifications and documentation from definition through productization

MatX designs hardware tailored for the world’s best AI models. They are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models.