- Collaborate with cross-functional teams to clarify design specifications.
- Architect and implement advanced micro-architectures adhering to performance metrics.
- Conduct block and system-level RTL coding, ensuring optimal performance.
Jobs ranked by similarity.
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, and are headquartered at the High Tech Campus in Eindhoven, Netherlands with offices across Europe.
They are looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. They aim to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity and AI acceleration. They empower engineers to design and deploy advanced systems with unmatched flexibility and performance, contributing to shaping the future through innovation.
Axelera AI is creating the next-generation AI platform to support anyone who wants to help advance humanity and improve the world. They are a world-class team of 220+ employees (including 49+ PhDs) with offices in multiple European countries and headquartered in Eindhoven, Netherlands.
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, with offices in multiple European countries and are headquartered in Eindhoven, Netherlands.
We are seeking talented individuals in the field of verification. FortifyIQ appears to be a growing company focused on high-performance silicon products.
Tenstorrent is innovating in AI technology, aiming for top performance, usability, and cost-effectiveness. Their team is developing a high-performance RISC-V CPU and is passionate about creating the best AI platform, valuing collaboration and problem-solving.
We're seeking an Embedded Systems Engineer with a passion for secure hardware design and cryptography. In this role, you’ll work at the intersection of hardware and software, contributing to the architecture and implementation of hybrid cryptographic systems that protect data at the chip level.