Collaborate with cross-functional teams to clarify design specifications.
Architect and implement advanced micro-architectures adhering to performance metrics.
Conduct block and system-level RTL coding, ensuring optimal performance.
Axelera AI is creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, they have raised a total of $120 million and have built a world-class team of 220+ employees, both remotely from 17 different countries and with offices in Europe.
Lead and grow the silicon logical (digital) design team.
Drive the translation of system and micro-architecture specifications into high-quality RTL implementations.
Own the end-to-end logical design execution for one or more SoCs, from concept through tape-out.
Axelera AI is creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. They have built a world-class team of 220+ employees remotely from 17 different countries and with offices in Europe.
Own organization-wide, multi-year technical direction across teams and silicon programs
Drive system and micro-architecture specs through high-quality RTL implementation
Partner across architecture, verification, physical design, software, product, and DFT
Axelera AI is creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. The company has a world-class team of 220+ employees and is headquartered at the High Tech Campus in Eindhoven, Netherlands.
Collaborate with RTL, verification, and physical design teams to integrate DFT solutions efficiently.
Support silicon bring-up and debug, helping to optimize test coverage and yield.
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, with offices in multiple European countries and are headquartered in Eindhoven, Netherlands.
Develop and execute verification plans for Processor units, ensuring all requirements and specifications are met.
Design and implement constrained random testbenches for processor core.
Collaborate with architecture, RTL design, and compiler teams to ensure thorough verification coverage.
Axelera AI is creating the next-generation AI platform to support anyone who wants to help advance humanity and improve the world. They are a world-class team of 220+ employees (including 49+ PhDs) with offices in multiple European countries and headquartered in Eindhoven, Netherlands.
Guarantee RTL designs are matching specifications and requirements
Define, implement and execute verification plans to ensure the designs meet quality and performance goals
Build and maintain automated verification environments
Axelera AI is creating the next-generation AI platform. They have a world-class team of 220+ employees, including 49+ PhDs, and are headquartered at the High Tech Campus in Eindhoven, Netherlands with offices across Europe.
Provide pre-sales technical leadership for Ciena's Interconnects portfolio across hyperscalers, OEMs, and AI/compute system partners.
Lead lab bring-up, debug, interoperability validation, configuration, and performance testing.
Translate customer system architectures and requirements into technical solutions and roadmap inputs.
Ciena is a global leader in high-speed connectivity committed to a people-first approach. Their teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging.
Participate in design development tasks throughout the IP development flow.
Develop the logic design, RTL coding, and simulation for an IP.
Apply strategies to write RTL and optimize the logic to qualify the design.
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity and AI acceleration. They empower engineers to design and deploy advanced systems with unmatched flexibility and performance, contributing to shaping the future through innovation.