Source Job

$136,000–$204,000/yr
US

  • Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks.
  • Work closely with analog and digital design teams on floor planning, pin placement, and signal distribution.
  • Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling.

Project Management

14 jobs similar to Staff Design Engineer, IC Layout

Jobs ranked by similarity.

$75,000–$95,000/yr
US

  • Design complex multi-layer PCBs using Altium, Cadence Allegro, or Siemens Xpedition for high-reliability aerospace products.
  • Enforce design rules for signal integrity, EMI/EMC, and manufacturability while collaborating with cross-functional engineering teams.
  • Own the complete fabrication and assembly documentation and serve as the go-to PCB expert for internal teams and external suppliers.

Astronics is a publicly traded global aerospace company that designs and manufactures advanced electronics for the aviation and defense markets. With over 50 years of history, the company is known for its collaborative culture and innovative solutions, serving Fortune 500 clients and military agencies worldwide.

US

  • Own RTL to GDS physical implementation flows including synthesis, floor-planning, place and route, clock tree synthesis, timing/power closure, EM/IR, and PD sign-off.
  • Own physical design and implementation of high-performance designs from block level to system level components.
  • Collaborate with micro-architects on performance, power, and area trade-offs and develop methodologies for physical implementation.

Baya Systems is a fast-moving Series B startup accelerating intelligent computing in the emerging chiplet era with software-driven fabric solutions and semiconductor IP. Built by serial entrepreneurs, it seeks energetic, dedicated individuals passionate about enabling innovation in the semiconductor industry.

$160,000–$240,000/yr
North America

  • Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
  • Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
  • Translate architectural specifications into clean, efficient, and scalable microarchitectures

We are a startup building foundational technology for AI data center clusters, backed by top-tier VC firms. We are a remote-first team of experienced builders based in the U.S. and Canada, with a culture of trust, integrity, and shared responsibility.

Global

  • Design and review transistor-level circuits for technical evaluation in an automated workflow.
  • Run SPICE simulations and verify accuracy of simulation outputs.
  • Identify and troubleshoot errors, providing structured feedback on tools and methodologies.

Terac builds the world's largest pool of vetted human experts for AI. Researchers and AI teams use Terac to recruit, screen, and pay study participants across industries and skill sets.

$95,630–$132,130/yr
North America

  • Develop custom IP for new features of the Kepler satellite digital payloads
  • Iterate on current DSP and interface designs to improve reliability
  • Work with IP core vendors and lead engineers to integrate new functionality and develop future satellite communications and network architecture

Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities. With 33 satellites launched to date, Kepler is a dedicated team of engineers building the next generation of spacecraft in an innovative and inclusive environment.

$121,800–$195,000/yr
US

  • Manage and grow strategic customer relationships within the semiconductor industry.
  • Combine consultative sales, technical understanding, and account development to drive revenue growth.
  • Oversee customer lifecycle activities including forecasting, quoting, order booking, and cross-functional collaboration.

Teradyne provides semiconductor test equipment and solutions, focusing on automated test equipment for the semiconductor industry. The role offers significant autonomy, exposure to complex capital equipment sales, and a collaborative, customer-focused culture.

$160,000–$240,000/yr
North America

  • Develop and maintain UVM-based verification environments for complex ASIC and FPGA designs.
  • Create and execute coverage-driven verification plans, test cases, and SystemVerilog Assertions.
  • Collaborate with RTL engineers to debug issues, analyze coverage, and drive verification to closure.

Delos Data builds foundational technology for performance, scalability, and resiliency in large-scale AI data center clusters. The startup is backed by top-tier VCs, led by experienced founders, and operates with a culture of unity, trust, and accountability across the U.S. and Canada.

India

  • Drive comprehensive SoC-level power and thermal management architecture for AI inference and training workloads.
  • Review and guide RTL implementation, collaborate with Physical Design teams, and refine floorplanning and multi-voltage domain structures.
  • Develop advanced Physical Design recipes and custom EDA workflows to achieve best-in-class PPA targets.

EnCharge AI develops next-generation AI platforms using novel in-memory-computing architecture. The company is an experienced team of AI researchers, silicon and systems engineers, and architects backed by leading investors.

US

  • Define, design, verify, and document ASIC/FPGA developments, including architecture, system simulation, and detailed design approaches.
  • Evaluate process flows such as synthesis, place and route, timing, and power utilization, and create test and simulation plans.
  • Lead technical proposals, review vendor capabilities, and serve as a consultant to management and customers on complex engineering applications.

General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products and services for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, alignment and transparency, and offer a flexible work environment.

North America Unlimited PTO

  • Design and implement FPGA code for Kepler's satellite digital payloads, focusing on DSP algorithms for software-defined radios or embedded systems.
  • Participate in all phases of FPGA design flow, from simulation and synthesis through timing closure and hardware testing.
  • Collaborate with lead engineers on communications architecture and integrate IP cores for new satellite constellation features.

Kepler Communications operates the first commercial optical data relay constellation, providing real-time, on-orbit connectivity for critical missions. With 33 satellites launched and a Great Place to Work certification for seven years, the company fosters a culture of bold thinkers and passionate problem-solvers.

Europe

  • Design and implement complex, configurable, low-latency RTL modules using SystemVerilog.
  • Develop digital logic for high-performance FPGA and ASIC applications, including signal processing and real-time control.
  • Collaborate with architects, verification engineers, and hardware specialists on quantum control platforms.

The company develops advanced control and measurement systems for quantum computing, enabling precise real-time control of complex quantum systems. It works in an international engineering environment focused on FPGA and ASIC-based platforms.

$150,000–$300,000/yr
Global

  • Building agents, environments, and post-training systems for real semiconductor design and verification workflows.
  • Designing rewards and evaluations that combine functional correctness with tool efficiency, robustness, and performance/power/area constraints.
  • Owning interactive environments where agents use EDA tools to modify designs, debug failures, and plan multi-step work.

Prime Intellect builds the open superintelligence stack, unifying compute, environments, evaluations, and deployment for frontier-scale AI post-training. The company has raised $150M in funding from top investors like Founders Fund and NVIDIA, fostering a culture of building at the intersection of research, infrastructure, and go-to-market.

$77,890–$118,999/yr
US

  • Work with multi-disciplined teams to develop substation physical layout drawings in 2D and 3D.
  • Plan and execute structural design deliverables, including foundation plans and structure details.
  • Provide guidance and mentorship to less experienced drafters and designers on drafting tools and design processes.

Sargent & Lundy provides comprehensive engineering, design, and project management services for power and energy projects. The company is committed to employee well-being and has been recognized with the Top Workplaces Culture Excellence Award for compensation and benefits.

US

  • Responsible for definition, design, verification and documentation for ASIC and FPGA developments.
  • Develops test and simulation plans, verifies results, and analyzes performance using SystemVerilog, UVM, and formal methods.
  • Supports the generation of technical engineering products throughout the ASIC/FPGA development life cycle.

General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions for defense and scientific missions. With a global team of 12,000+ professionals, they value trust, honesty, and transparency, offering a flexible work environment.